Xilinx Virtex-4 RocketIO User Manual page 308

Appendix C: Dynamic Reconfiguration Port
Table C-16: Dynamic Reconfiguration Port Memory Map: MGTB Address 45–49
Bit
45
15
14
13
12
11
RESERVED
10
[10:0]
9
8
7
6
5
(4)
4 TXPHASESEL
(5)
3 TXPHASESEL
2 RESERVED
(3)
1 PMACLKENABLE
0 PMACOREPWRENABLE
Notes:
1. The default X depends on the operation. See
2. This register value must equal the register value at address 0x59, bit[15:12] on MGTB. The attribute RXOUTDIV2SEL sets both registers upon configuration, but
must be written to separately using the DRP.
3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
4. Applies to MGTA only.
5. Applies to MGTB only.
308
Def 46 Def
0 0
0 0
0 0
0 0
0 0
1 0
0 0
RESERVED
0 0
RESERVED
[14:0]
0 0
0 0
1 0
0 0
0 0
0 0
1 1
1 TXPD 0
Table C-28, page 320 for details.
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Address
47 Def 48
RXCRCINITVAL
N/A
[15:0] [31:16]
Def 49
RESERVED
RXOUTDIV2SEL
(2)
[3:0]
N/A
RXCTRL1
(3)
[9:0]
RESERVED
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
(1)
Def
0
X
X
X
X
1
0
0
0
0
0
0
X
X
1
0