Figure 2-22: Flow Chart Of Receiver Reset Sequence Where Rx Buffer Is Bypassed - Xilinx Virtex-4 RocketIO User Manual
Multi-gigabit transceiver
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- Configuration user manual (114 pages) ,
- User manual (176 pages)
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Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RX_SYSTEM_RESET
system_reset==0
RX_PMA_RESET
RXPMARESET==1 for
3 RXUSRCLK cycles
RX_WAIT_LOCK
rx_usrclk_stable==1 && RXLOCK==1 for
16K (16 x 1024) REFCLK cycles
RXLOCK==0
RX_SYNC
RXSYNC==1 for
64 synchonization cycles
RXLOCK==0
RX_PCS_RESET
RXRESET==1 for
3 RXUSRCLK cycles
RXLOCK==0
RX_WAIT_PCS
5 RXUSRCLK cycles
RXLOCK==0
RX_ALMOST_READY
rx_error==0 && RXLOCK==1
for 64 RXUSRCLK cycles
RXLOCK==0
RX_READY
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rx_sync_cnt==16 &&
rx_error==1 &&
RXLOCK==1
rx_sync_cnt < 16 && rx_error==1 && RXLOCK==1
rx_error==1 && RXLOCK==1
Resets
ug076_ch2_23_060606
97
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