Xilinx Virtex-4 RocketIO User Manual page 298

Appendix C: Dynamic Reconfiguration Port
Table C-6: Dynamic Reconfiguration Port Memory Map: MGTA Address 54–58
Bit
54
15
TXPRE_TAP_DAC
14
[2:0]
13
12 RESERVED
(2)
11 TXHIGHSIGNALEN
10 RESERVED
9
8
TXTERMTRIM
[3:0]
7
6
5 TXASYNCDIVIDE[1]
(3)
4 TXSLEWRATE
3
TXPOST_PRDRV_DAC
2
(2)
[2:0]
1
0 TXDAT_PRDRV_DAC[2]
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. TXSLEWRATE is set to 0 by default. It must be set to 1 for all serial rates below 6.25 Gb/s. The RocketIO Wizard sets this attribute to 1.
4. Although this is a 9-bit register, the user can only control bits [2:0]. See
be specified as a 9-bit value. The RXAFEEQ[8:3] bits are unused and can be set to 0.
298
(1)
Def 55 Def
0 0
0 0
0 0
0 0
1 0
1 0
1 0
1 0
UNUSED
[15:0]
0 0
0 0
X 0
0 0
1 0
1 0
1 0
(2)
1 0
Table C-28, page 320e for details.
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Address
(1)
56 Def
0
RXFETUNE
(2)
[1:0]
1
X
RXRCPADJ
X
(2)
[2:0]
X
RESERVED
N/A
[1:0]
0
0
0
0
RXAFEEQ
0
(4)
[8:0]
0
0
0
0
"Receive Equalization" in Chapter 4
57 Def 58
0
0
0
0
0
0
0
0
RXEQ TXCRCINITVAL
[47:32] [31:16]
0
0
0
0
0
0
0
0
for details. Note that in a UCF file RXAFEEQ must
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A