Figure 2-12: Transmit Clocking Decision Flow (Page 1 Of 2) - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
TXOUTDIV2SEL
VCO rate = line
Set TXPLLNDIVSEL
= VCO rate/refclk
TXOUTCLK1_USE_SYNC
YES
TXCLKMODE[3:0]
(cont'd on next page)

Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2)

80
START
NO
is line
rate >5G
YES is line rate
>2.5G
YES
TXOUTDIV2SEL
= /1 = /2
VCO rate = line
rate/2 rate
NO
(1)
YES
= FALSE
NO
Use 8B/10B?
Use
64B/66B?
YES
TXCLKMODE[3:0]
= 0100
= 1001
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NO
NO
is line rate
>1.25G
YES
is line rate
>0.625G
YES
TXOUTDIV2SEL TXOUTDIV2SEL
= /4 = /8
VCO rate = 2*line VCO rate = 4*line
rate rate
1. Modify refclk frequency for valid (8, 10, 16, 20, 32, 40)
TXPLLNDIVSEL values. The lower value
generates better performance.
2. Channel Bonding, Clock Corection, 64B66B,
and 8-byte fabric interface are not available
in low latency mode.
3. TXOUTCLK1 and TXOUTCLK2 are never the
same in the mode when TXOUTCLK1_USE_SYNC
is set to false regardless of low latency mode
usage. There is no use model that needs these to
be the same.
4. Max serial rate for 1-byte I/F is 2.5 Gb/s.
Max serial rate for 2-byte I/F is 5.0 Gb/s.
5. This mode requires that USRCLK be provided by
the fabric.
6. When Channel Bonding, the RXUSRCLK must be
generated from the fabric for all bonded MGTs.
7. 64B/66B encoding/decoding is not supported.
NO
Use SONET
or no
(7)
encoding
TXCLKMODE[3:0]
= 1110
NO
line rate
<0.625G
TXOUTDIV2SEL
= /16
VCO rate = 8*line
rate
ug076_ch2_09a_061507
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R