And Tx_Align_Err Is Not Used - Xilinx Virtex-4 RocketIO User Manual

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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
TXLOCK==0
TXLOCK==0
TXLOCK==0
TXLOCK==0
Figure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
It is assumed that the frequency of TXUSRCLK is slower than the frequency of
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state. An exception of this requirement is the wait time between assertions of
TXLOCK and TXSYNC signals, from TX_WAIT_LOCK to TX_SYNC states. Use the
specified TXUSRCLK2 in this step.
See Figure 8-15, "TXSYNC Timing," page 214
cycles and the 64 synchronization clock cycles specified in this block.
tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
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TX_SYSTEM_RESET
system_reset==0
TX_PMA_RESET
TXPMARESET==1 for
3 TXUSRCLK cycles
TX_WAIT_LOCK
tx_usrclk_stable==1 && TXLOCK==1
for 12,000 TXUSRCLK2 cycles
TX_SYNC
TXSYNC==1 for
64 synchronization clock cycles
TX_PCS_RESET
TXRESET==1 for
3 TXUSRCLK cycles
TX_WAIT_PCS
5 TXUSRCLK cycles
TX_READY

and tx_align_err Is Not Used

regarding the 12,000 TXUSRCLK2
Resets
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