Figure A-2: Mgt Timing Relative To Clock Edge; Timing Diagram And Timing Parameter Tables - Xilinx Virtex-4 RocketIO User Manual

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Timing Diagram and Timing Parameter Tables

Figure A-2
Table A-2
tools relative to the clocks given in
are synchronous to each clock. (No signals are synchronous to REFCLK or TXUSRCLK.)
•
•
•
•
•
•
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
illustrates the timing relationships.
1
T
x GWH
CLOCK
T
GCCK
CONTROL
INPUTS
T
GCKCO
CONTROL
OUTPUTS
T
GDCK
DATA
INPUTS

Figure A-2: MGT Timing Relative to Clock Edge

through Table A-7 list the timing parameters as reported by the implementation
Table A-2, "RocketIO DCLK Switching Characteristics," page 276
Table A-3, "RocketIO RXCRCCLK Switching Characteristics," page 276
Table A-4, "RocketIO TXCRCCLK Switching Characteristics," page 277
Table A-5, "RocketIO RXUSRCLK2 Switching Characteristics," page 278
Table A-6, "RocketIO RXUSRCLK2 Switching Characteristics," page 278
Table A-7, "RocketIO TXUSRCLK Switching Characteristics," page 280
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Timing Diagram and Timing Parameter Tables
2
T
x GWL
T
GCKC
T
GCKD
Table A-1, page 271, along with the MGT signals that
ug076_apA_02_032304
275