Xilinx Virtex-4 RocketIO User Manual page 16

Figure 3-2: Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 3-3: RX Ring Buffer Half-Full Upon Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 3-4: RX Ring Buffer Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-5: Fabric Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 3-6: PCS Bypass Byte Mapping, 8-Byte External Fabric Width . . . . . . . . . . . . . . 107
Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width . . . . . . . . . . . . . . 107
Figure 3-8: 8B/10B Parallel-to-Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-9: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-10: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-11: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-12: 8B/10B Comma Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-13: 6-Bit Alignment Mux Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-14: SONET Alignment Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-15: SONET Alignment Sequence (4-Byte External Data Interface Width) . . . 119
Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width) . . . 120
Figure 3-17: Comma Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 3-18: RXSLIDE Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 3-19: Effects of CCCB_ARBITRATOR_DISABLE = TRUE. . . . . . . . . . . . . . . . . . 130
Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses . . . . . . . . . . . . 131
Figure 3-21: XC4VFX20/XC4VFX60 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 3-22: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-23: Digital Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 3-24: PCS RXCLK Generation, Buffered Mode (Green) . . . . . . . . . . . . . . . . . . . . 136
Chapter 4: PMA Analog Design Considerations
Figure 4-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 4-2: 3-Tap Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 4-4: TX with Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 144
Figure 4-6: TX with Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 4-7: RX after 36 Inches FR4 and Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 146
Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer. . . . . . . . . . . 148
Figure 4-9: OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Chapter 5: Cyclic Redundancy Check (CRC)
Figure 5-1: 32-bit CRC Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 5-2: 64-Bit to 32-Bit Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 5-3: Max Data Rate Example (64-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 5-4: Max Data Rate Example (32-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example . . . . . . . . . 160
Figure 5-6: CRC Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16 www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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