Xilinx Virtex-4 RocketIO User Manual page 37

R
The RocketIO MGT transceiver consists of the Physical Media Attachment (PMA) and
Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES),
TX and RX input/output buffers, clock generator, and clock recovery circuitry. The PCS
contains the 8B/10B encoder/decoder and the ring buffer supporting channel bonding
and clock correction. Refer to
FPGA interface signals.
Table 1-3
widths of one, two, and four bytes (lower speeds) or four and eight bytes (higher speeds)
are selectable for the various protocols.
Table 1-3: MGT Protocol Settings
Standard/
(1)
Application
Custom 6.25 Gb/s
4X Fibre Channel
10G Fibre Channel
over 4 links
XAUI
Serial RapidIO Type 3
Serial RapidIO Type 2
Serial RapidIO Type 1
Serial ATA Type 2
Serial ATA Type 1
PCI Express
Infiniband
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
lists supported standards and certain values used to support that standard. Data
Data Rate RocketIO MGT
(Gb/s) Coding
6.25 8B/10B
4.25 8B/10B
3.1875 8B/10B
3.125 8B/10B
3.125 8B/10B
2.5 8B/10B
1.25 8B/10B
3.0 8B/10B
1.5 8B/10B
2.5 8B/10B
2.5 8B/10B
www.xilinx.com
Basic Architecture and Capabilities
Figure 1-1 showing the MGT top-level block diagram and
Reference Clock
Frequency (F )
in
312.5
212.5
159.375
312.5
312.5
250.0
(5)
250.0
300.0
300.0
250.0
250.0
Parallel Data
Parallel Data
Width
Frequency (MHz)
(bytes)
8 78.13
4 156.25
4 106.25
2 212.5
8 39.84
4 79.69
8 39.06
4 78.13
2 156.25
8 39.06
4 78.13
2 156.25
2 125.00
1 250.00
2 62.50
1 125.00
8 37.50
4 75.00
2 150
2 75.00
1 150.00
2 125.00
1 250.00
2 125.00
1 250.00
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