Clk_Cor_Seq_1_Mask, Clk_Cor_Seq_2_Mask; Clk_Cor_Seq_Len Attributes - Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver
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Table 3-14: Definition of Clock Correction Sequence Bits 9-0
Table 3-15
value, and the parallel data interface, and how each corresponds with the other.
Table 3-15: Clock Correction Sequence/Data Correlation

CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_MASK,

CLK_COR_SEQ_LEN Attributes

These attributes are used to correctly define the clock correction sequences. The
CLK_COR_SEQ_LEN attribute defines the length of the clock correction action and is used
in conjunction with CLK_COR_SEQ_*_MASK attributes to define the length of the
sequence match. Valid sequence lengths are 1, 2, 3, 4, and 8. In the case of 8 bytes, the
CLK_COR_SEQ_2_USE must be set to FALSE.
clock correction sequence. Note that the CLK_COR_SEQ_1_MASK is set to indicate a
2-byte sequence as well.
Table 3-16: Clock Correction Mask Example Settings (No Mask)
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
CLK_COR_SEQ_*_*[9:8]
XX
0
0
32
1
Raw RXDATA[9:8]
0
0
40
0
XX
1
0
40
1
Raw RXDATA[9:8]
1
0
40
0
XX
1
1
40
1
RXDISPERR, RXCHARISK
1
1
40
0
is an example of data 11-bit attribute setting, the character value, CHARISK
Attribute Setting
CLK_COR_SEQ_1_1 = 00110111100
CLK_COR_SEQ_1_2 = 00010010101
CLK_COR_SEQ_1_3 = 00010110101
CLK_COR_SEQ_1_4 = 00010110101
Attribute
CLK_COR_SEQ_1_1
CLK_COR_SEQ_1_2
CLK_COR_SEQ_1_MASK
CLK_COR_SEQ_LEN
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CLK_COR_SEQ_*_*[7:0]
Raw RXDATA[7:0]
Raw RXDATA[7:0]
Raw RXDATA[7:0]
Raw RXDATA[7:0]
8B/10B Decoded RXDATA[7:0]
8B/10B Decoded RXDATA[7:0]
Character
CHARISK
K28.5
1
D21.4
0
D21.5
0
D21.5
0
Table 3-16
shows the settings for a 2-byte
Setting
Defines a K28.5.
00110111100
Defines a D21.4.
00010010101
Check compare first 2 bytes.
1100
Complete sequence is 2 bytes.
2
Clock Correction
TXDATA (hex)
BC
95
B5
B5
Definition
125

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