Xilinx Virtex-4 RocketIO User Manual page 231

R
Table 8-14: Latency for Use Model TX_3A
Notes:
1. T
2. T
3. 1 UI = 1/3.125e9 = 320 ps
4. 64B/66B encoding/decoding is not supported.
As summarized
interface. This would reduce the fabric interface latency and the skew. User logic can still
have a 2-byte data path, with the final input stage to the MGT being a fabric mux that
muxes two 2-byte words from the user logic into a 4-byte word to input to TXDATA.
This incurs one additional TXUSRCLK2 latency, as detailed below. In this implementation,
the worst case skew is reduced to ~3.53 UI (1.13 ns), while the latency increases to 98.56 ns.
This implementation provides a good trade-off of latency versus skew.
Table 8-15: Latency for Use Model TX_3A Using a 4-Byte Fabric Interface)
Notes:
1. T
2. 1 UI = 1/3.125e9 = 320 ps
3. 64B/66B encoding/decoding is not supported.
RX
Since this is a channel-bonded system, the RX buffer should be used. From a system
perspective, a user might decide not to use clock correction in order to minimize latency,
using the RXRECCLK1/RXRECCLK2 to clock the RXUSRCLK and RXUSRCLK2 ports.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Transmit Blocks
Fabric Interface (2 Byte)
Encoding (8B/10B)
TX Buffer
PMA Interface
(4)
64B/66B Format (Bypass)
PMA Register
PISO
Total:
= T = T
PMA TXCLK0 PCS TXCLK
= 1/156.25 MHz = 6.4 ns
TXUSRCLK2
inTable 8-15, a further step a user might take is to go to a 4-byte fabric
Transmit Blocks
User Fabric 2-byte to 4-byte MUX
Fabric Interface (4 Byte)
Encoding (8B/10B)
TX Buffer
PMA Interface
(3)
64B/66B Format (Bypass)
PMA Register
PISO
Total:
= T = T
PMA TXCLK0 PCS TXCLK
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Example of a Reduced-Latency System
Latency
2 TXUSRCLK2 + 1 TXUSRCLK
2 TXUSRCLK
0 TXUSRCLK / PCS TXCLK
0 PCS TXCLK
0 PCS TXCLK
1 PMA TXCLK0
68 UI
= 1/156.25 MHz * 2 = 12.8 ns
TXUSRCLK
Latency
1 TXUSRCLK2
1 TXUSRCLK2 + 1 TXUSRCLK
2 TXUSRCLK
0 TXUSRCLK / PCS TXCLK
0 PCS TXCLK
0 PCS TXCLK
1 PMA TXCLK0
68 UI
= T = 1/156.25 MHz
TXUSRCLK TXUSRCLK2
Latency (ns)
25.60
25.60
0
0
0
12.80
21.76
85.76
Latency (ns)
12.8
25.60
25.60
0
0
0
12.80
21.76
98.56
* 2 = 12.8 ns
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