Xilinx Virtex-4 RocketIO User Manual page 92

Chapter 2: Clocking, Timing, and Resets
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See
requirement.
Below are the steps describing the flow chart in
1.
2.
3.
4.
5.
6.
92
used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
In synchronous systems like the GPON application, where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to
♦
Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦
Digital CDR Mode:
!system_reset && RXLOCK == 1
"RX Reset Sequence Background," page 100
TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
TXSYNC == 0
TX_WAIT_LOCK: Stall until TXLOCK is High and until the clocks on TXUSRCLK and
TXUSRCLK2 are stable (tx_usrclk_stable == 1), then wait for 12,000 TXUSCLK2 cycles
and go to TX_SYNC state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 0
TX_SYNC: Assert TXSYNC for 64 synchronization cycles. If TXLOCK is deasserted,
go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 1
TX_PCS_RESET: Assert TXRESET for three TXUSRCLK cycles. If TXLOCK is
deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 1
TXSYNC == 0
TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If
TXLOCK is deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
www.xilinx.com
for information on the 16K REFCLK cycles
Figure 2-17:
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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