Xilinx Virtex-4 RocketIO User Manual page 58

Chapter 1: RocketIO Transceiver Overview
Table 1-12: RocketIO MGT PCS Attributes (Continued)
Attribute
Clocks
RXCLK0_FORCE_PMACLK
RX_CLOCK_DIVIDER
RXASYNCDIVIDE
RXUSRDIVISOR
TXCLK0_FORCE_PMACLK
TX_CLOCK_DIVIDER
TXASYNCDIVIDE
Buffers
RX_BUFFER_USE
TX_BUFFER_USE
58
Type
FALSE/TRUE. Determines if the PMA RXCLK0 or the RXUSRCLK is
chosen as the source for the PCS RXCLK in conjunction with
RX_CLOCK_DIVIDER and LOOPBACK[0].
FALSE:
If RX_CLOCK_DIVIDER ≠ 00, PCS RXCLK is sourced by
♦
RXUSRCLK
If RX_CLOCK_DIVIDER = 00, PCS RXCLK is sourced by
♦
Boolean
PMA RXCLK0
If LOOPBACK[0] = 1 and RX_CLOCK_DIVIDER = 00,
♦
PCS RXCLK is sourced by PMA TXCLK0 (to facilitate parallel
loopback mode)
TRUE: PCS RXCLK is sourced by PMA RXCLK0
See Chapter 2, "Clocking, Timing, and Resets"
page 74 for more details.
2-bit Controls the clock tree in the PCS. See
Binary and Resets" for more details.
2-bit Sets up the internal clocks. See
Binary Resets" for setting to the correct value.
Selects the divisor for the clock received from the PMA. The divided
Integer
clock becomes RXRECCLK1. See
FALSE/TRUE. Determines if the PMA TXCLK0 or the TXUSRCLK is
chosen as the source for the PCS TXCLK in conjunction with
TX_CLOCK_DIVIDER.
FALSE:
If TX_CLOCK_DIVIDER ≠ 00, PCS TXCLK is sourced by
♦
TXUSRCLK
Boolean
If TX_CLOCK_DIVIDER = 00, PCS TXCLK is sourced by
♦
PMA TXCLK0
TRUE: PCS TXCLK is sourced by PMA TXCLK0
See Chapter 2, "Clocking, Timing, and Resets"
page 75 for more details.
2-bit Controls the clock tree in the PCS. See
Binary and Resets" for more details.
2-bit Sets up the internal clocks. See
Binary Resets" for setting to the correct value.
TRUE/FALSE. Controls bypassing the RX ring buffer.
Boolean
TRUE: RX ring buffer is used
FALSE: RX ring buffer is bypassed
TRUE/FALSE. Controls bypassing the TX buffer.
Boolean
TRUE: TX buffer is used
FALSE: TX buffer is bypassed
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Description
and Figure 2-7,
Chapter 2, "Clocking, Timing,
Chapter 2, "Clocking, Timing, and
Figure 2-5.
and Figure 2-8,
Chapter 2, "Clocking, Timing,
Chapter 2, "Clocking, Timing, and
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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