Figure 6-1: Mgt Tile Power And Serial I/O Pins - Xilinx Virtex-4 RocketIO User Manual

Chapter 6: Analog and Board Design Considerations
164
AVCCAUXRX
VTRXA
RXAP
RXAN
AVCCAUXTX
VTTXA
TXAP
TXAN
VTTXB
TXBP
TXBN
AVCCAUXRXB
VTRXB
RXBP
RXBN
AVCCAUXMGT

Figure 6-1: MGT Tile Power and Serial I/O Pins

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RXA CDR and
RXA
Deserializer
TXA
TXA/B CMU
and Serializer
TXB
REFCLK
Circuitry and
Bias
RXB CDR and
RXB
Deserializer
MGT Bias Circuits
and MGTCLK
Input Buffer
Virtex-4 RocketIO MGT User Guide
V
CCINT
PCS,
Control and
Configuration
UG076_ch6_07_072007
UG076 (v4.1) November 2, 2008
R