Xilinx Virtex-4 RocketIO User Manual page 319

R
Table C-27: Dynamic Reconfiguration Port Memory Map: MGTB Address 7C–7F
Bit
7C
15
RXDATA_SEL
[15:14]
14
13
TXDATA_SEL
[13:12]
12
11 RESERVED
10
9
8
CLK_COR_MIN_LAT
[5:0]
7
6
5
4 RESERVED
3 PCS_BIT_SLIP
2 DIGRX_SYNC_MODE
1
DIGRX_FWDCLK
[1:0]
0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Def 7D Def
0
0
0
0
0
0
0
0
UNUSED
N/A
[15:0]
0
0
0 CCCB_ARBITRATOR_DISABLE
0
0
0
0
0
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Address
7E Def
RESERVED
[7:0]
N/A
UNUSED
[1:0]
OPPOSITE_SELECT
POWER_ENABLE
RESERVED
[2:0]
Memory Map
7F Def
RESERVED
TX_BUFFER_USE
RX_BUFFER_USE
CHAN_BOND_SEQ_LEN
[2:0]
CHAN_BOND_SEQ_2_USE
CHAN_BOND_ONE_SHOT
N/A
CHAN_BOND_MODE
[1:0]
CHAN_BOND_LIMIT
[5:0]
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