Xilinx Virtex-4 RocketIO User Manual page 313

R
Table C-21: Dynamic Reconfiguration Port Memory Map: MGTB Address 5E–62
Bit
(1)
5E Def
15 0
14 0
RESERVED
13 0
[4:0]
12 0
11 0
10 1
TXPRE_PRDRV_DAC
9 1
(2)
[2:0]
8 1
7 TXPRE_TAP_PD 1
6 0
TXPRE_TAP_DAC
[4:3]
5 0
4 RESERVED 0
3 X
2 X
TXCLKMODE
[3:0]
1 X
0 X
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. RXSELDACFIX[3:0] on MGTB is composed of bits [14:11] at address 0x62 in this table.
4. RXSELDACTRAN[4:0] on MGTB is composed of bits [10:6] at address 0x62 in this table.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
5F Def 60
RXBYPASS_CAL
RXFDET_HYS_CAL
[2:0]
RXFDET_LCK_CAL
[2:0]
RESERVED
N/A
RXFDET_HYS_SEL
[15:0]
[2:0]
RXFDET_LCK_SEL
[2:0]
RXVCO_CTRL_ENABLE
RXCYCLE_LIMIT_SEL
[1:0]
Table C-28, page 320 for details.
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Address
Def 61
(2)
N/A
MCOMMA_32B_VALUE
[15:0]
(2)
00
(2)
Memory Map
Def 62 Def
RXDIGRESET 0
0
RXFECONTROL2
0
(2,3)
[2:0]
0
(2,3)
RXCPTST 0
(2,4)
RXPDDTST 1
(2,4)
RXACTST 0
(2,4)
RXAFETST 0
N/A
0
RXFECONTROL1
(2,4)
[1:0]
0
(2)
RXLKAPD 0
(2)
RXRSDPD 0
0
RESERVED
0
[2:0]
0
RXPD 0
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