Xilinx Virtex-4 RocketIO User Manual page 90

Chapter 2: Clocking, Timing, and Resets
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In some systems, there might not be a feedback mechanism that can generate the
tx_align_err signal for the reset sequence. In those cases, users can implement the flow
illustrated in
strictly required, but it ensures stability in the user's system, preventing the system from
restarting while transmitting data.
Refer to the following points in conjunction with this figure:
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90
TX_WAIT_LOCK: Stall until TXLOCK is High and until the clocks on TXUSRCLK and
TXUSRCLK2 are stable (tx_usrclk_stable == 1), then wait for 12,000 TXUSCLK2 cycles
and go to TX_SYNC state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 0
TX_SYNC: Assert TXSYNC for 64 synchronization cycles. If TXLOCK is deasserted,
go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == X
TXSYNC == 1
TX_PCS_RESET: Assert TXRESET for three TXUSRCLK cycles. If TXLOCK is
deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 1
TXSYNC == 0
TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If
TXLOCK is deasserted, go back to TX_WAIT_LOCK state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
TX_ALMOST_READY: Wait for 64 TXUSRCLK cycles with TXLOCK High for this
amount of time. This is to ensure that the TX MGT is stable after start-up and ready for
data transmission. If TXLOCK is deasserted, go back to TX_WAIT_LOCK state. If there
is a TX alignment error from the user's application as a result of TXSYNC not being
successful, apply TXSYNC by cycling back to the TX_SYNC state. If this step occurs 16
times as monitored by the tx_sync_cnt counter, apply a TXPMARESET by cycling back
to TX_PMA_RESET state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
TX_READY: If the TX phase alignment is successful for some time, then the TX link is
ready.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
Figure 2-17 when the TX buffer is bypassed. The tx_align_err signal is not
The flow chart uses TXUSRCLK and TXUSRCLK2 as reference to the wait time for
each state. Do not use TXUSRCLK and TXUSRCLK2 as the clock source for this block;
these clocks might not be present during some states. Use a free-running clock (for
example, the system's clock) and make sure that the wait time for each state equals the
specified number of TXUSRCLK and TXUSRCLK2 cycles.
www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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