Rx Latency; Rx Low Latency Buffered Mode; Overview; Clocking - Xilinx Virtex-4 RocketIO User Manual

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RX Latency

To minimize the latency in the RX, the phase discrepancy between the PCS RXCLK and
PMA RXCLK0 can be minimized by the RX phase alignment circuitry. This allows the user
to bypass portions of the PCS or the entire PCS and thereby reduce the latency through the
RX side of the MGT.
In cases where the RX buffer is bypassed, the phase alignment circuitry is necessary to
align the PCS RXCLK and PMA RXCLK0.
The most frequently anticipated use cases are mentioned below. The user can use these
examples as a guide to determine a custom path if required.

RX Low Latency Buffered Mode

Overview

For this mode, the RXSYNC functionality is not required. This results in bypassed
functionality without the need for synchronizing the PCS and PMA clocks.

Clocking

There is no particular clocking restriction in this mode. If there are multiple synchronized
channels, the same USRCLK and USRCLK2 should be input to all the MGTs so that they
are all in phase with each other.
As noted earlier, if channel bonding is being used, the internal PCS dividers cannot be
used, and an external RXUSRCLK must be provided.
To use the internal PCS dividers for RXUSRCLK (do not use for channel bonding because
bonded GT11s must share the same RXUSRCLK):
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To provide for an external RXUSRCLK:
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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
If 4-byte mode is required, RX_CLOCK_DIVIDER = 11.
If 2-byte mode is required, RX_CLOCK_DIVIDER = 01.
If 1-byte mode is required, RX_CLOCK_DIVIDER = 10.
Set RXCLK0_FORCE_PMACLK to TRUE.
Set RX_CLOCK_DIVIDER = 00 and provide the appropriate frequency clock at the
RXUSRCLK port. This might require the use of an additional DCM or PMCD.
Set RXCLK0_FORCE_PMACLK to FALSE.
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RX Latency
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