Xilinx Virtex-4 RocketIO User Manual page 339

R
Running Disparity Control (table)
RX After 24 Inches FR4 and Maximal Pre-
146
Emphasis (figure)
RX After 24 Inches FR4 and Minimal Pre-
Emphasis (figure) 145
RXBUFERR 133
152
RXDCCOUPLE
152
RXPD
43
RXSYNC
S
Selecting the External Configuration (ta-
104
ble)
Selecting the Internal Configuration (ta-
ble) 104
Serial I/O Description 139
235
Signal integrity
Signal Values
for a Channel Bonding Skew (table)
132
for a Pointer Difference Status (table)
132
for Event Indication (table)
Signal Values for a Pointer Difference Sta-
132
tus (table)
Simulation and Implementation
Simulation Models 179
HSPICE 180
179
SmartModels
Single-Ended Trace Geometry (figure)
177
SMA Connectors 255
SMT DC Blocking Capacitor Design Ex-
267
ample
SMT Pads 247
SMT XENPAK70 Connector Design Ex-
262
ample
SMT XFP Connector Design Example
Status and Event Bus 132
Event Indication 133
132
Status Indication
Stripline Edge-Coupled Differential Pair
(figure) 178
Summary of Guidelines 257
Symbol Alignment see Comma Detection
116
T
Termination 171
171
Termination (power)
Time Domain Reflectometry (TDR)
275
Timing Diagram
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
110
Timing Parameter Tables
Timing Parameters
Clock Pulse Width
Clock to Output Delays
Input Setup/Hold Times Relative to
Clock 274
Top-Level Architecture
Transmit and Receive
Total Jitter (DJ + RJ)
241
Traces, PCB
Characteristic impedance
237
Clock
241
Geometry
Loss, simulating
Microstrip
Plane splits
243
Routing
242
Stripline
Transceiver Location and Package Pin Re-
lation 186
Transitions, PCB
245
and TDR
Bends in Microstrip/Stripline
133
definition of
Design of 245
179
Excess capacitance/inductance
Microstrip/Stripline Bends
Cut-outs
Jog-outs
Mitered
245
SMT pads
245
Vias
Transmit Architecture
Transmit Termination
TX PMA Attribute Values (table)
TXCHARDISPMODE
111
TXCHARISK
263
TXRUNDISP 111
TXRXPD 152
Tyco Z-PACK HM-Zd Connector Design
264
Example
U
User Guide Conventions
Comma Definition
Port and Attribute Names
User Guide Organization
245
www.xilinx.com
275
274
274
274
101
101
30
241
243
242
243
245
235
245
252
252
252
252
101
171
69
110
30
30
28
V
Valid Data and Control Characters,
283
8B/10B
Valid Data Characters (table)
245
Vias
Voltage Regulation 166
283
339