Xilinx Virtex-4 RocketIO User Manual page 187

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Table 7-4: LOC Grid and Package Pins Correlation for FF1152
XC4VFX40-FF1152
LOC
Constraint
MGT TXP
GT11_X0Y0 105B AL34 AM34 AP32
GT11_X0Y1 105A AJ34
GT11_X0Y2
103B Y34
GT11_X0Y3 103A V34
GT11_X0Y4 102B F34
GT11_X0Y5 102A D34
GT11_X0Y6 – –
GT11_X0Y7 – –
GT11_X0Y8 – –
GT11_X0Y9 – –
GT11_X1Y0 110B AH1
GT11_X1Y1 110A AF1
GT11_X1Y2
112B U1
GT11_X1Y3 112A R1
GT11_X1Y4 113B C1
GT11_X1Y5 113A A4
GT11_X1Y6 – –
GT11_X1Y7 – –
GT11_X1Y8 – –
GT11_X1Y9 – –
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
TXN RXP RXN MGT TXP
AP31 106B
AK34 AF34 AG34 106A
AA34 AC34 AD34 105B
W34 R34 T34 105A
G34 J34 K34 103B
E34 A31 A32 103A
– – – 102B
– – – 102A
– – – –
– – – –
AJ1 AL1 AM1 109B
AG1 AC1 AD1 109A
V1 Y1 AA1 110B
T1 M1 N1 110A
D1 F1 G1 112B
A3 A7 A6 112A
– – – 113B
– – – 113A
– – – –
– – – –
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Transceiver Location and Package Pin Relation
XC4VFX60-FF1152
TXN RXP RXN MGT TXP
AP21 AP20 AP18 AP17
AP23 AP22 AP26 AP25
AL34 AM34 AP32 AP31
AJ34 AK34 AF34 AG34
Y34 AA34 AC34 AD34
V34 W34 R34 T34
F34 G34 J34 K34
D34 E34 A31 A32
– – – –
– – – –
AP11 AP12 AP14 AP15
AP9 AP10 AP6 AP7
AH1 AJ1 AL1 AM1
AF1 AG1 AC1 AD1
U1 V1 Y1 AA1
R1 T1 M1 N1
C1 D1 F1 G1
A4 A3 A7 A6
– – – –
– – – –
XC4VFX100-FF1152
TXN RXP RXN
106B AP21 AP20 AP18
106A AP23 AP22 AP26
105B AL34 AM34 AP32
105A AJ34 AK34 AF34
103B Y34 AA34 AC34 AD34
103A V34 W34 R34
102B F34 G34 J34
102A D34 E34 A31
101B A25 A26 A28
101A A23 A24 A20
109B AP11 AP12 AP14
109A AP9 AP10 AP6
110B AH1 AJ1 AL1
110A AF1 AG1 AC1
112B U1 V1 Y1
112A R1 T1 M1
113B C1 D1 F1
113A A4 A3 A7
114B A13 A12 A10
114A A15 A14 A18
AP17
AP25
AP31
AG34
T34
K34
A32
A29
A21
AP15
AP7
AM1
AD1
AA1
N1
G1
A6
A9
A17
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