Xilinx Virtex-4 RocketIO User Manual page 317

R
Table C-25: Dynamic Reconfiguration Port Memory Map: MGTB Address 72–76
Bit
(1)
72 Def
15 0
RXFETUNE
(2)
[1:0]
14 1
CLK_COR_SEQ_2_MASK
13 X
RXRCPADJ
12 X
(2)
[2:0]
11 X
10 1
RESERVED
[1:0]
9 1
8 0
7 0
CLK_COR_SEQ_2_4
6 0
5 0
RXAFEEQ
4 0
(3)
[8:0]
3 0
2 0
1 0
0 0 CLK_COR_SEQ_2_3[10]
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. Although this is a 9-bit register, the user can only control bits [2:0]. See
be specified as a 9-bit value. The RXAFEEQ[8:3] bits are unused and can be set to 0.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
73 Def
CLK_COR_SEQ_1_MASK
[3:0]
N/A
CLK_COR_SEQ_1_4
[10:0]
CLK_COR_SEQ_1_3[10]
Table C-28, page 320 for details.
"Receive Equalization" in Chapter 4
www.xilinx.com
Address
74 Def 75
[3:0]
UNUSED
N/A
[15:0]
[10:0]
for details. Note that in a UCF file RXAFEEQ must
Memory Map
Def 76
0
0
CHAN_BOND_SEQ_2_MASK
[3:0]
0
0
0
0
0
0
0
CHAN_BOND_SEQ_2_4
0
[10:0]
0
0
0
0
0
0 CHAN_BOND_SEQ_2_3[10]
Def
N/A
317