Pcs Bypass Byte Mapping - Xilinx Virtex-4 RocketIO User Manual

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PCS Bypass Byte Mapping

When bypassing the entire RX PCS using an internal data width of 32 bits (RXDATA_SEL
= 01), bytes are ordered as shown in
applies only to this one specific configuration. A 40-bit internal datapath setting or any
reduced-latency setting other than RXDATA_SEL = 01 does not follow this mapping.
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•
Note:
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
8 Byte External Fabric Width (64 bits),
RXINTDATAWIDTH = 2'b10, RXDATAWIDTH = 2'b11:
Use Byte 7, Byte 6, Byte 5, Byte 4, Byte 3, Byte 2, Byte 1, Byte 0 mapping
63
7
Byte 7
RXDATA[57:56]
56
55
7
Byte 6
RXDATA[51:48]
48
47
7
Byte 5
RXDATA[45:40]
40
39
7
Byte 4
RXDATA[39:32]
32
31
7
Byte 3
RXDATA[25:24]
24
23
7
Byte 2
RXDATA[19:16]
16
15
7
Byte 1
RXDATA[13:8]
8
7
7
Byte 0
RXDATA[7:0]
0
Figure 3-6: PCS Bypass Byte Mapping, 8-Byte External Fabric Width
4 Byte External Fabric Width (32 bits),
RXINTDATAWIDTH = 2'b10, RXDATAWIDTH = 2'b10:
Use Byte 3, Byte 2, Byte 1, Byte 0 mapping
31
7
Byte 3
RXDATA[25:24]
24
23
7
Byte 2
RXDATA[19:16]
16
15
7
Byte 1
RXDATA[13:8]
8
7
7
Byte 0
RXDATA[7:0]
0
Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width
External data width of 1 and 2 bytes is not supported in this mode.
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Figure 3-6 through
6 5
RXCHARISK[6] RXRUNDISP[6]
4 3
RXCHARISK[5] RXRUNDISP[5]
2 1
RXCHARISK[4] RXRUNDISP[4]
0
6 5
RXCHARISK[2] RXRUNDISP[2]
4 3
RXCHARISK[1] RXRUNDISP[1]
2 1
RXCHARISK[0] RXRUNDISP[0]
0
(Figure
6 5
RXCHARISK[2] RXRUNDISP[2]
4 3
RXCHARISK[1] RXRUNDISP[1]
2 1
RXCHARISK[0] RXRUNDISP[0]
0
Bus Interface
Figure 3-7. Note that this mapping
(Figure
4 3
RXDATA[55:52]
2 1
RXDATA[47:46]
0
4 3
RXDATA[23:20]
2 1
RXDATA[15:14]
0
ug076_ch3_27_090805
3-7):
4 3
RXDATA[23:20]
2 1
RXDATA[15:14]
0
ug076_ch3_26_091406
3-6):
0
0
0
0
0
0
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