Xilinx Virtex-4 RocketIO User Manual page 137

R
Table 3-26: Digital Receiver Attribute Settings (Line Rates ≤ 1.25 Gb/s) (Continued)
Notes:
1. The clock generated by the digital receiver is not a recommended DCM clock input because the clock
2. Ensure RXRESET is not synchronous with RXRECCLK1. RXRESET resets the 1XCLK, 2XCLK and
3. Ensure that the transmitter and receiver are driven by the same clock source and use internal dividers
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Digital Receiver Attribute
RXCLK0_FORCE_PMACLK
DIGRX_SYNC_MODE
RX_CLOCK_DIVIDER
RXUSRCLK2
does not meet the jitter specification of the DCM.
4XCLK and consequently the RXRECLK1 that is derived from the Digital receiver.
on RXUSRCLK as shown in
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Description (Buffered Mode)
TRUE: The PMA RXCLK0 drives the PCS RXCLK.
FALSE: Phase Aligner circuit is disabled.
Sets RXUSRCLK rate. PCS RXCLK is driven by the PMA RXCLK0
(1X CLK).
00: Use external RXUSRCLK port.
11: Divide by 1 for a 4-byte fabric interface.
01: Divide by 2 for a 2-byte fabric interface.
10: Divide by 4 for a 1-byte fabric interface.
(2)
Sourced by RXRECCLK1
(3)
TXOUTCLK1 , MGT Reference clock
The ring buffer aligns PCS RXCLK and
(3)
RXUSRCLK/RXUSRCLK
Figure 3-24.
Digital Receiver
or derivatives of RXRECCLK2
(3)
.
(3)
,
137