Xilinx Virtex-4 RocketIO User Manual page 40

Chapter 1: RocketIO Transceiver Overview
Table 1-4: RocketIO MGT CRC Ports
Port
RXCRCCLK
RXCRCDATAVALID
RXCRCDATAWIDTH
RXCRCIN
RXCRCINIT
RXCRCINTCLK
RXCRCOUT
RXCRCPD
RXCRCRESET
TXCRCCLK
TXCRCDATAVALID
TXCRCDATAWIDTH
TXCRCIN
TXCRCINIT
TXCRCINTCLK
TXCRCOUT
TXCRCPD
TXCRCRESET
40
I/O Port Size
I 1 Receiver CRC logic clock.
I 1 Signals that the RXCRCIN data is valid.
Determines the data width of the RXCRCIN:
000
001
010
I 3
011
100
101
110
111
I 64 Receiver CRC logic input data.
I 1 When set to logic 1, CRC logic initializes to the RXCRCINITVAL.
I 1 Receiver CRC/FPGA fabric interface clock.
Receiver CRC output data. This bus must be inverted to obtain
O 32
the valid CRC value.
I 1 Powers down the RX CRC logic when set to logic 1.
I 1 Resets the RX CRC logic when set to logic 1.
I 1 Transmitter CRC logic clock.
I 1 Signals that the TXCRCIN data is valid when set to a logic 1.
Determines the data width of the TXCRCIN:
000
001
010
I 3
011
100
101
110
111
I 64 Transmitter CRC logic input data.
I 1 When set to logic 1, CRC logic initializes to the TXCRCINITVAL.
I 1 Transmitter CRC/FPGA fabric interface clock.
Transmitter CRC output data. This bus must be inverted to
O 32
obtain the valid CRC value.
I 1 Powers down the TX CRC logic when set to logic 1.
I 1 Resets the TX CRC logic when set to a logic 1.
www.xilinx.com
Definition
= 8 bits RXCRCIN[63:56]
= 16 bits RXCRCIN[63:48]
= 24 bits RXCRCIN[63:40]
= 32 bits RXCRCIN[63:32]
= 40 bits RXCRCIN[63:24]
= 48 bits RXCRCIN[63:16]
= 56 bits RXCRCIN[63:8]
= 64 bits RXCRCIN[63:0]
= 8 bits TXCRCIN[63:56]
= 16 bits TXCRCIN[63:48]
= 24 bits TXCRCIN[63:40]
= 32 bits TXCRCIN[63:32]
= 40 bits TXCRCIN[63:24]
= 48 bits TXCRCIN[63:16]
= 56 bits TXCRCIN[63:8]
= 64 bits TXCRCIN[63:0]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R