Xilinx Virtex-4 RocketIO User Manual page 306

Appendix C: Dynamic Reconfiguration Port
Table C-14: Dynamic Reconfiguration Port Memory Map: MGTA Address 7C–7F
Bit
7C Def
15
RXDATA_SEL
[1:0]
14
13
TXDATA_SEL
[1:0]
12
11 RESERVED
10
9
8
CLK_COR_MIN_LAT
N/A
[5:0]
7
6
5
4 RESERVED
3 PCS_BIT_SLIP
2 DIGRX_SYNC_MODE
1
DIGRX_FWDCLK
[1:0]
0
Notes:
1. The default X depends on the operation. See
2. This register value must equal the register value at address 0x6D, bit[14:11] on MGTA. The attribute RXOUTDIV2SEL sets both registers upon configuration, but
must be written to separately using the DRP.
3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
306
Address
(1)
7D Def
X
X
RXOUTDIV2SEL
(2)
[3:0]
X
X
X
X
RXPLLNDIVSEL
[3:0]
X
X
0
RESERVED
[1:0]
0
X CCCB_ARBITRATOR_DISABLE
X
RXLOOPFILT
(3)
[3:0]
X
X
RXDIGRX 0
RESERVED 0
Table C-28, page 320 for details.
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7E Def
RESERVED
[7:0]
N/A
UNUSED
[1:0]
OPPOSITE_SELECT
POWER_ENABLE
RESERVED
[2:0]
Virtex-4 RocketIO MGT User Guide
7F Def
RESERVED
TX_BUFFER_USE
RX_BUFFER_USE
CHAN_BOND_SEQ_LEN
[2:0]
CHAN_BOND_SEQ_2_USE
CHAN_BOND_ONE_SHOT
N/A
CHAN_BOND_MODE
[1:0]
CHAN_BOND_LIMIT
[5:0]
UG076 (v4.1) November 2, 2008
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