Xilinx Virtex-4 RocketIO User Manual page 315

R
Table C-23: Dynamic Reconfiguration Port Memory Map: MGTB Address 68–6C
Bit
68 Def
15 RESERVED
14
13
12
11
10 N/A
RXVCODAC_INIT
(1)
[9:0]
9
8
7
6
5
4 0
RXSLOWDOWN_CAL
(1)
[1:0]
3
0
(1)
2 BYPASS_FDET
1 N/A
RXLOOPCAL_WAIT
(1)
[1:0]
0
Notes:
1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
69 Def
MCOMMA_32B_VALUE
N/A
[31:16]
RXDCCOUPLE
www.xilinx.com
Address
6A Def 6B
RXCMADJ
N/A
[1:0]
0
0
0
RXCDRLOS CLK_COR_SEQ_2_3
[5:0] [9:0]
0
0
0
RESERVED N/A
0
UNUSED 0
0
0
CLK_COR_SEQ_2_2
RXLKADJ
[10:5]
0
[4:0]
0
0
Memory Map
Def 6C Def
CLK_COR_SEQ_1_3
[9:0]
N/A N/A
CLK_COR_SEQ_1_2
[10:5]
315