Figure 2-1: Mgt Column Clocking - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
GREFCLK
REFCLKSEL
Not
Connected
REFCLK
GREFCLK
REFCLKSEL
MGTCLK
REFCLK
GREFCLK
REFCLKSEL
Not
Connected
REFCLK
GREFCLK
REFCLKSEL
MGTCLK
REFCLK
62
XC4VFX60 Reference Clock Selection
GT11CLK_MGT
Reference Clock
Routing
GT11CLK_MGT
Reference Clock
Routing
GT11CLK_MGT
Reference Clock
Routing
GT11CLK_MGT
Reference Clock
Routing
Note: (1) The PMA RXBCLK clock path is not supported.

Figure 2-1: MGT Column Clocking

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Receive
REFCLK2
Dividers
PLL A
REFCLK1
RXAPMACLKSEL
Dividers
Shared
Transmit
PLL
Dividers
TXABPMACLKSEL
Receive
PLL B
Dividers
RXBPMACLKSEL
PMA RXBCLK
Receive
REFCLK2
Dividers
PLL A
REFCLK1
RXAPMACLKSEL
Dividers
Shared
Transmit
PLL
Dividers
TXABPMACLKSEL
Receive
PLL B
Dividers
RXBPMACLKSEL
PMA RXBCLK
Receive
REFCLK2
Dividers
PLL A
REFCLK1
RXAPMACLKSEL
Dividers
Shared
Transmit
PLL
Dividers
TXABPMACLKSEL
Receive
PLL B
Dividers
RXBPMACLKSEL
PMA RXBCLK
REFCLK2 Receive
Dividers
PLL A
REFCLK1
RXAPMACLKSEL
Dividers
Shared
Transmit
PLL
Dividers
TXABPMACLKSEL
Receive
PLL B
Dividers
RXBPMACLKSEL
PMA RXBCLK
PMA RXCLK A
PMA TXCLK A
Tile 1
PMA TXCLK B
PMA RXCLK B
(1)
PMA RXCLK A
PMA TXCLK A
Tile 2
PMA TXCLK B
PMA RXCLK B
(1)
PMA RXCLK A
PMA TXCLK A
Tile 3
PMA TXCLK B
PMA RXCLK B
(1)
PMA RXCLK A
PMA TXCLK A
Tile 4
PMA TXCLK B
PMA RXCLK B
(1)
ug076_ch2_01_071807
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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