Xilinx Virtex-4 RocketIO User Manual page 47

R
Table 1-7: RocketIO MGT General Ports
Port
LOOPBACK
POWERDOWN
GREFCLK
REFCLK1
REFCLK2
Table 1-8: RocketIO MGT Dynamic Reconfiguration Ports
Port
DADDR
DCLK
DEN
DI
DO
DRDY
DWE
Table 1-9: RocketIO MGT Communications Ports
Port
COMBUSOUT
COMBUSIN
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
I/O Port Size
Selects the two loopback test modes. These modes are PCS
I 2 parallel, and pre-driver serial loopback. See
Digital Design Considerations"
Shuts down entire PCS transceiver when set to logic 1.
I 1
This input is asynchronous. PMA powerdown is controlled via
attributes.
Reference clock (alternate clock not recommended for over 1G
I 1
operation).
I 1 Reference clock (low jitter input clock).
I 1 Reference clock (low jitter input clock).
I/O Port Size
Dynamic Reconfiguration Port address bus. See
I 8
"Dynamic Reconfiguration Port."
I 1 Dynamic Reconfiguration Port bus clock.
Dynamic Reconfiguration Port bus enable when set to a
I 1
logic 1.
I 16 Dynamic Reconfiguration Port input data bus.
O 16 Dynamic Reconfiguration Port output data bus.
Indicates that the Dynamic Reconfiguration Port output data is
O 1
valid when raised to a logic 1.
Dynamic Reconfiguration Port write enable when set to a
I 1
logic 1.
I/O Port Size
Connects to the COMBUSIN of the other GT11 in the tile to
O 16
allow proper simulation of shared clocks and PLLs.
Connects to the COMBUSOUT of the other GT11 in the tile to
I 16
allow proper simulation of shared clocks and PLLs.
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Available Ports
Definition
Chapter 3, "PCS
for details.
Definition
Appendix C,
Definition
47