Xilinx Virtex-4 RocketIO User Manual page 304

Appendix C: Dynamic Reconfiguration Port
Table C-12: Dynamic Reconfiguration Port Memory Map: MGTA Address 72–76
Bit
(1)
72 Def
15 0
14 0
CLK_COR_SEQ_2_MASK
13 0
12 0
11 0
10 0
9 0
RESERVED
8 0
[14:0]
7 0
CLK_COR_SEQ_2_4
6 0
5 0
4 0
3 0
2 1
1 1
(2)
0 TXCPSEL X CLK_COR_SEQ_2_3[10]
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
304
73 Def
CLK_COR_SEQ_1_MASK
[3:0] [3:0]
N/A
CLK_COR_SEQ_1_4
[10:0] [10:0]
CLK_COR_SEQ_1_3[10]
Table C-28, page 320 for details.
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Address
74 Def 75
RESERVED
[14:0]
N/A
(2)
RXCPSEL
(1)
Def 76
0
0
CHAN_BOND_SEQ_2_MASK
[3:0]
0
0
0
0
0
0
0
CHAN_BOND_SEQ_2_4
0
[10:0]
0
0
0
1
1
X CHAN_BOND_SEQ_2_3[10]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A