Use Models; Skew; Reset - Xilinx Virtex-4 RocketIO User Manual

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Use Models

Table 8-7: TX Use Models: Low-Latency Buffered Mode w/out Channel Deskew
TX_1A
Internal PCS clock dividers
TX_1B to derive TXUSRCLK from
TXUSRCLK2
TRUE
TX_1C
External TXUSRCLK
TX_1D
Notes:
1. All cases addressed assume a 4-byte fabric width. Refer to section
a. If 2-byte mode is required and the TXUSRCLK dividers are to be used, TX_CLOCK_DIVIDER = 01.
b. If 1-byte mode is required and the TXUSRCLK dividers are to be used, TX_CLOCK_DIVIDER = 10.
c. If external TXUSRCLK is to be used, leave TX_CLOCK_DIVIDER = 00 and provide the appropriate frequency clock at the
TXUSRCLK port.
2. 64B/66B encoding/decoding is not supported.
3. TXSCRAM64B66BUSE and TXGEARBOX64B66BUSE are always to be set to the same value.

Skew

Without using the TXSYNC alignment circuitry, the native skew of the A and B MGTs is
4 UI. Because the reset of the parallel clock dividers in the transmit data path occurs after
the initial divide-by-two where the serial clock is one-fourth the line rate, the deassertion
of TXPMARESET is completely asynchronous with regard to this serial clock domain.
The 4 UI accuracy assumes that the individual MGTA and MGTB TXPMARESETs do not
contain additional sources of skew from fabric routing.

Reset

TXRESET across multiple channels should always be synchronized to minimize skew
across channels.
Refer to section
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
No Bypass. 10GBASE-R
Encode and GearBox
and 64B/66B Scrambler
No Bypass. 8B/10B
Encode
10GBASE-R GearBox
or
and 64B/66B Scrambler
Bypass
8B/10B and 64B/66B
Encoding Bypass
"Resets" in Chapter 2
www.xilinx.com
Transmit Latency and Output Skew
PORTS
0 1 1 1
NOT
1 0 0 0
USED
Tie to
logic 0
0 1 0 0
0 0 0 0
"Clocking," page 198 for 2 byte or 1 byte fabric width.
for details on resetting multiple channels.
ATTRIBUTES
TRUE
00
00 TRUE or or
FALSE
11
199