Xilinx Virtex-4 RocketIO User Manual page 302

Appendix C: Dynamic Reconfiguration Port
Table C-10: Dynamic Reconfiguration Port Memory Map: MGTA Address 68–6C
Bit
68 Def
15 RESERVED
14
13
12
11
10 N/A
RXVCODAC_INIT
(2)
[9:0]
9
8
7
6
5
4
0
RXSLOWDOWN_CAL
(2)
[1:0]
3
0
(2)
2 RXBYPASS_FDET
1 N/A
RXLOOPCAL_WAIT
(2)
[1:0]
0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. Although there is an open-loop divider for each MGT, both attributes map into MGTA locations in the DRP Memory Map:
TXOUTDIV2SEL (for MGTB) Reg 0x6A [14:11]
TXOUTDIV2SEL (for MGTA) Reg 0x7A [15:12]
302
69 Def
TXOUTDIV2SEL
MCOMMA_32B_VALUE
N/A
[31:16]
Table C-28, page 320 for details.
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Address
(1)
6A Def 6B
RESERVED 0
X
X
(3)
[3:0]
X
X
CLK_COR_SEQ_2_3
[9:0]
1
0
0
0
0
TXCTRL1
(2)
[9:0]
0
0
X
CLK_COR_SEQ_2_2
[10:5]
X
0
RESERVED 0
Def 6C
CLK_COR_SEQ_1_3
[9:0]
N/A
CLK_COR_SEQ_1_2
[10:5]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A