Fabric Interface Functionality - Xilinx Virtex-4 RocketIO User Manual

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Fabric Interface Functionality

The number of RXUSRCLK2 cycles required to read RXDATA varies depending on the
interface mode (width). The MGT's internal datapath is 4 bytes wide; therefore, in 2-byte or
1-byte mode, "future" information is overloaded onto the unused bytes.
summarizes this operation of the fabric interface.
graphically, as a user might view it at the ports of the MGT.
Table 3-3: Fabric Interface Functionality
RXUSRCLK2
Notes:
1. User accesses lower 4 bytes.
2. User accesses lower 2 bytes.
3. User accesses lower 1 byte
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Cycle
8-Byte
Cycle 0 RXDATA[63:0]
Cycle 1 Same as Cycle 0
Cycle 2 Same as Cycle 0
Cycle 3 Same as Cycle 0
Cycle 4 Same as Cycle 0
Cycle 5 Same as Cycle 0
Cycle 6 Same as Cycle 0
Cycle 7 Same as Cycle 0
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Figure 3-5
Interface Mode (Width)
(1)
4-Byte 2-Byte
32'h00000000,
32'h00000000,
RXDATA[31:16],
RXDATA[31:0]
RXDATA[15:0]
32'h00000000,
Same as Cycle 0
16'h0000,
RXDATA[31:16]
Same as Cycle 0 Same as Cycle 0
Same as Cycle 0 Same as Cycle 1
Same as Cycle 0 Same as Cycle 0
Same as Cycle 0 Same as Cycle 1
Same as Cycle 0 Same as Cycle 0
Same as Cycle 0 Same as Cycle 1
Bus Interface
Table 3-3
illustrates the operation
(2) (3)
1-Byte
32'h00000000,
RXDATA[31:24],
RXDATA[23:16],
RXDATA[15:8],
RXDATA[7:0]
32'h00000000,
8'h00,
RXDATA[31:24],
RXDATA[23:16],
RXDATA[15:8]
32'h00000000,
8'h00,
8'h00,
RXDATA[31:24],
RXDATA[23:16]
32'h00000000,
8'h00,
8'h00,
8'h00,
RXDATA[31:24]
Same as Cycle 0
Same as Cycle 1
Same as Cycle 2
Same as Cycle 3
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