Xilinx Virtex-4 RocketIO User Manual page 18

Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C . . . . . . . . . . . . . 227
Figure 8-22: RXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Section II:
Board Level Design
Chapter 9: Methodology Overview
Figure 9-1: Two RocketIO MGTs Interconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Chapter 10: PCB Materials and Traces
Figure 10-1: Differential Edge-Coupled Centered Stripline . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-2: Differential Edge-Coupled Offset Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-3: Centered Broadside-Coupled Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 10-4: Differential Microstrip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Chapter 11: Design of Transitions
Figure 11-1: TDR Signature of Shunt Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-2: TDR Signature of Series Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-3: Integration of Normalized TDR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad . . . . . . . . . . . . . . . 247
Figure 11-5: Transition Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out . . . . . . . . . . . . . . . 248
Figure 11-7: Return Loss Comparison Between 0402 Pad Structures . . . . . . . . . . . . . . . . 248
Figure 11-8: Return Loss Comparison Between 0402 Pad Structures
on Log (Frequency) Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 11-9: TDR Results Comparing 0402 Pad Structures
with Excess Capacitance Reduced from 840 fF to 70 fF . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 11-10: Differential Via Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 11-11: Differential GSSG Via in 16-layer PCB from Pins L11 and L6 . . . . . . . . . 251
Figure 11-12: Simulated Return Loss Comparing Differential and Common-Mode
Losses for L11 and L6 GSSG Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 11-13: Example Design for 90 Degree Bends in Traces . . . . . . . . . . . . . . . . . . . . . 252
Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs . . . . . . . . . . . . . . . . . . 253
Figure 11-15: Simulated Return Loss of 45 Degree Bends with Jog-Outs . . . . . . . . . . . . 253
Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs . . . . . . . . 254
Figure 11-17: 90° Mitered Turns without and with Jog-Outs. . . . . . . . . . . . . . . . . . . . . . . 254
Figure 11-18: Measured TDR of Differential Pair with Four Mitered 90° Turns,
with and without Jog-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 12: Guidelines and Examples
Figure 12-1: Differential Via Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 12-2: BGA Escape Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
18 www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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