Xilinx Virtex-4 RocketIO User Manual page 303

R
Table C-11: Dynamic Reconfiguration Port Memory Map: MGTA Address 6D–71
Bit
(1)
6D Def
15 RESERVED 0
14 X
13 X
RXOUTDIV2SEL
(2)
[3:0]
12 X
11 X
10 1
9 0
8 0
7 0
6 0
RXCTRL1
(3)
[9:0]
5 0
4 0
3 X
2 X
1 0
0 RESERVED 0
Notes:
1. The default X depends on the operation. See
2. This register value must equal the register value at address 0x7D, bit[15:12] on MGTA. The attribute RXOUTDIV2SEL sets both registers upon configuration, but
must be written to separately using the DRP.
3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Address
6E Def 6F Def
N/A N/A
Table C-28, page 320 for details.
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70 Def
(3)
BYPASS_CAL
FDET_HYS_CAL
[2:0]
FDET_LCK_CAL
[2:0]
N/A
FDET_HYS_SEL
[2:0]
FDET_LCK_SEL
[2:0]
(3)
VCO_CTRL_ENABLE
0
CYCLE_LIMIT_SEL
(3)
[1:0]
0
Memory Map
71 Def
PCOMMA_32B_VALUE
N/A
[15:0]
303