Use Models - Xilinx Virtex-4 RocketIO User Manual

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Use Models

Table 8-8: TX Use Models: Low-Latency Buffered Mode with Channel Deskew
TX_2A
Internal PCS clock
TX_2B
dividers to derive
TRUE
TXUSRCLK from
TX_2C
TXUSRCLK2
TX_2D
TX_2E
TX_2F
TRUE External TXUSRCLK
TX_2G
TX_2H
Notes:
1. All cases addressed assume a fabric width of 4 bytes.
a. For Use Models TX_2A -D, if 2-byte mode is required, TX_CLOCK_DIVIDER = 01.
b. For Use Models TX_2A -D, if 1-byte mode is required, TX_CLOCK_DIVIDER = 10.
c. For Use Models TX_2E-H, the appropriate frequency clock should be provided at the TXUSRCLK port for 2-byte or 1-byte mode.
This could require the use of an additional DCM or PMCD.
2. GREFCLK is used as clock synchronization source.
3. TXSCRAM64B66BUSE and TXGEARBOX64B66BUSE are always to be set to the same value.
4. MGTA/MGTB Register 0x43[7]=1 always for TX Low Latency. This can be accomplished with a Read-Modify-Write Operation
via the Dynamic Reconfiguration Port. Alternatively, this can be achieved by adding the constraint TXCLK0_INVERT_PMALEAF =
"TRUE" to the UCF file. The COREGen RocketIO Wizard generates this constraint when choosing to bypass the buffer to enable Low
Latency.
5. 64B/66B encoding/decoding is not supported.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
No Bypass. 10GBASE-R
Encode and 64B/66B
GearBox and Scrambler
No Bypass. 8B/10B Encode
64B/66B GearBox and
Scrambler Bypass
8B/10B and 64B/66B
Encoding Bypass
No Bypass. 10GBASE-R
Encode and 64B/66B
GearBox and Scrambler
No Bypass. 8B/10B Encode
64B/66B GearBox and
Scrambler Bypass
8B/10B and 64B/66B
Encoding Bypass
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Transmit Latency and Output Skew
PORTS
0 1 1 1
1 0 0 0
REQ'D
0 1 0 0
0 0 0 0
0 1 1 1
1 0 0 0
REQ'D
0 1 0 0
0 0 0 0
ATTRIBUTES
FALSE
00 TRUE 11
(Note 4)
FALSE
FALSE
or
00 00
(Note 4)
TRUE
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