Xilinx Virtex-4 RocketIO User Manual page 65

R
Table 2-3: Clock Selection for Three PLLs in a Tile
Attribute String
RXPMACLKSEL (MGTA)
Value
REFCLK1 column bus
REFCLK1
supplies MGTA RX PLL
REFCLK2 column bus
REFCLK2
supplies MGTA RX PLL
GREFCLK column bus
(2)
GREFCLK
supplies MGTA RX PLL
Notes:
1. This attribute is only contained in MGTB for both MGTs in the tile.
2. Should only be used for 1 Gb/s or slower serial rates.
The MGTCLK inputs drive the reference clocks that are low-jitter and must be used for the
fastest data rates (over 1 Gb/s).
Additionally, one of the FPGA fabric (global) clocks can be used as a reference clock for
single tiles at lower data rates (1 Gb/s or lower) via the GREFCLK input. If a fabric clock
needs to be routed along the REFCLK1 and REFCLK2 column busses, then the reference
clock input of the GT11CLK_MGT must be used.
Clocks derived from the MGT or from the MGT clock input can be forwarded to the FPGA
global clock resources. See
The clock recovered from MGTB can be fed to GT11CLK to be used as a reference clock for
that tile or other tiles in the column. This implementation using the MGT's RXMCLK
output and the GT11CLK module's RXBCLK input is shown in
an unsupported test feature and is not recommended for normal operating modes.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RXPMACLKSEL (MGTB)
REFCLK1 column bus
supplies MGTB RX PLL
REFCLK2 column bus
supplies MGTB RX PLL
GREFCLK column bus
supplies MGTB RX PLL
"GT11CLK_MGT and Reference Clock Routing," page
www.xilinx.com
Clock Distribution
TXPMACLKSEL
(MGT Tile – MGT A and MGT B)
REFCLK1 column bus supplies TX
PLL for both MGTs in the tile
REFCLK2 column bus supplies TX
PLL for both MGTs in the tile
GREFCLK column bus supplies TX
PLL for both MGTs in the tile
Figure 2-1, page
(1)
63.
62. This is
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