Xilinx Virtex-4 RocketIO User Manual page 183

R
VHDL Test Bench : EX_ROCBUF_tb.vhd
For further details, refer to the software user manual Synthesis and Verification Design Guide
available at http://www.xilinx.com/support/sw_manuals/xilinx7/download/.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
I : in std_logic;
O : out std_logic
);
end component;
begin
U1 : ROCBUF port map (I => SRP, O => GSR);
//dummy process
COUNTER : process (CLOCK, ENABLE,RESET)
begin
....................................
...................................
end process COUNTER;
end A
entity EX_ROCBUF_tb is
end EX_ROCBUF_tb;
architecture behavior of EX_ROCBUF_tb
declare component EX_ROCBUF
declare signals
begin
EX_ROCBUF_inst: EX_ROCBUF PORT MAP(
CLOCK => CLOCK,
ENABLE => ENABLE,
SRP => SRP,
RESET => RESET,
COUT => COUT
);
Clk_generation: process
Begin
...........................
End process
reset <= '1', '0' after CLK_PERIOD * 30;
SRP <= '1', '0' after CLK_PERIOD * 25;
end
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