Xilinx Virtex-4 RocketIO User Manual page 19

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Figure 12-3: Via Structures for BGA Adjacent SIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 12-4: XENPAK70 Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 12-5: SMT XFP Connector Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 12-6: SMT XFP Connector Return Loss Simulation Results . . . . . . . . . . . . . . . . . 264
Figure 12-7: Tyco Z-PACK HM-Zd Press-Fit Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 12-8: Tyco Z-PACK HM-Zd Press-Fit Connector Internals . . . . . . . . . . . . . . . . . . 265
Figure 12-9: Tyco Z-PACK HM-Zd Press-Fit Connector Design Example . . . . . . . . . . . 266
Figure 12-10: SMT DC Blocking Capacitor Design Example . . . . . . . . . . . . . . . . . . . . . . 267
Section III:
Appendixes
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Multi-Gigabit Transceiver Block Diagram . . . . . . . . . . . . . . . . . . 273
Figure A-2: MGT Timing Relative to Clock Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Appendix B: 8B/10B Valid Characters
Appendix C: Dynamic Reconfiguration Port
Appendix D: Special Analog Functions
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO
Transceiver Design Migration
Figure E-1: Reference Clock Selection for Each Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure E-2: Virtex-II, Virtex-II Pro, and Virtex-4 Power Supply Filtering . . . . . . . . . . . 329
Appendix F: References
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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