Figure 2-19: Flow Chart Of Receiver Reset Sequence Where Rx Buffer Is Used - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets
Below are the steps describing the flow chart in
1.
2.
94
RX_SYSTEM_RESET
system_reset==0
RX_PMA_RESET
RXPMARESET==1 for
3 RXUSRCLK cycles
RX_WAIT_LOCK
rx_usrclk_stable==1 && RXLOCK==1 for
16K (16 x 1024) REFCLK cycles
RXLOCK==0
RX_PCS_RESET
RXRESET==1 for
3 RXUSRCLK cycles
RXLOCK==0
RX_WAIT_PCS
5 RXUSRCLK cycles
RXLOCK==0
RX_ALMOST_READY
rx_error==0 && RXLOCK==1
for 64 RXUSRCLK cycles
RXLOCK==0
RX_READY

Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used

RX_SYSTEM_RESET: Upon RX system reset on this block, go to the RX_PMA_RESET
state.
RXPMARESET == 0
RXRESET == 0
RX_PMA_RESET: Assert RXPMARESET for three RXUSRCLK cycles.
RXPMARESET == 1
RXRESET == X
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rx_pcs_reset_cnt==16 &&
rx_error==1 &&
RXLOCK==1
rx_pcs_reset_cnt <16 && rx_error==1 && RXLOCK==1
rx_error==1 && RXLOCK==1
Figure 2-19:
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
ug076_ch2_20_062806