Xilinx Virtex-4 RocketIO User Manual page 335

Index
Numerics
10-Bit RX Data Map with 8B/10B By-
passed (figure) 112
10-Bit TX Data Map with 8B/10B By-
111
passed (figure)
16-bit Transmission, Hold CRC, and Resi-
due of 8-Bit Example 160
16-bit Transmission, Hold CRC, and Resi-
due of 8-Bit Example (figure)
4-Byte Serial Structure (figure)
64-Bit to 32-Bit Core Interface
64-Bit to 32-Bit Core Interface (figure)
8B/10B
Encoder 109
Valid Characters 283
117
8B/10B Alignment
8B/10B Bypassed Signal Significance (ta-
113
ble)
8B/10B Comma Detection Example (fig-
117
ure)
8B/10B Comma Symbol Configuration
(table) 118
8B/10B Decoder Byte-Mapped Status
118
Flags(table)
8B/10B Parallel-to-Serial Conversion (fig-
ure) 108
8B/10B Signal Definitions (table)
A
172
AC and DC Coupling
AC-Coupled Serial Link (figure)
Additional Resources 29
122
ALIGN_COMMA_WORD
ALIGN_COMMA_WORD Functionality
122
(table)
Alignment 122
ALIGN_COMMA_WORD
All Combinations of Data Width and Ac-
tive Data Bus Bits (table) 157
Analog and Board Design Considerations
163
Append/Remove Idle Clock Correction
123
Attributes
ALIGN_COMMA_WORD
CCCB_ARBITRATOR_DISABLE
54
CHAN_BOND_LIMIT
CHAN_BOND_MODE 54
CHAN_BOND_ONE_SHOT
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
CHAN_BOND_SEQ_1_1, 2, 3, 4
CHAN_BOND_SEQ_1_MASK
CHAN_BOND_SEQ_2_1, 2, 3, 4
CHAN_BOND_SEQ_2_MASK
CHAN_BOND_SEQ_2_USE
CHAN_BOND_SEQ_LEN
CLK_COR_8B10B_DE
CLK_COR_MAX_LAT
160
CLK_COR_MIN_LAT
108
CLK_COR_SEQ_1_1, 2, 3, 4
156
CLK_COR_SEQ_1_MASK
156
CLK_COR_SEQ_2_1, 2, 3, 4
CLK_COR_SEQ_2_MASK
CLK_COR_SEQ_2_USE
CLK_COR_SEQ_LEN
CLK_CORRECT_USE
COMMA_10B_MASK
COMMA32
DCDR_FILTER
DEC_MCOMMA_DETECT
DEC_PCOMMA_DETECT
DEC_VALID_COMMA_ONLY
DIGRX_FWDCLK
DIGRX_SYNC_MODE
ENABLE_DCDR
110
FDET_HYS_CAL
FDET_HYS_SEL
FDET_LCK_CAL
FDET_LCK_SEL
GT11_MODE
173
LOOPCAL_WAIT
MCOMMA_32B_VALUE
MCOMMA_DETECT
PCOMMA_32B_VALUE
PCOMMA_DETECT
PCS_BIT_SLIP
122
PMACOREPWRENABLE
POWER_ENABLE
RX_BUFFER_USE
RX_CLOCK_DIVIDER
RXAFEEQ
RXASYNCDIVIDE
RXBY_32
56
RXCDRLOS
54
RXCLK0_FORCE_PMACLK
RXCLKMODE
RXCMADJ
54
RXCPSEL
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54
55
55
55
55
55
55
55
55
55
56
56
56
56
56
55
56
56
59
57
57
57
59
59
59
50
50
50
50
60
50
57
56
57
57
57
52
53
58
58
50
58
59
52
58
51
52
50
48
RXCRCCLOCKDOUBLE
48
RXCRCSAMECLOCK
RXDATA_SEL 59
RXDCCOUPLE 50
59
RXDIGRESET
59
RXDIGRX
50
RXFDET_HYS_CAL
RXFDET_HYS_SEL 50
50
RXFDET_LCK_CAL
50
RXFDET_LCK_SEL
52 53
RXLKADJ
,
RXLOOPCAL_WAIT 50
RXOUTDIV2SEL 51
52
RXPD
51
RXPLLNDIVSEL
51
RXPMACLKSEL
RXRECCLK1_USE_SYNC 51
RXRSDPD 52
58
RXUSRDIVISOR
50
RXVCODAC_INIT
59
SAMPLE_8X
SH_CNT_MAX 57
57
SH_INVALID_CNT_MAX
58
TX_BUFFER_USE
58
TX_CLOCK_DIVIDER
TXABPMACLKSEL 52
TXASYNCDIVIDE 58
58
TXCLK0_FORCE_PMACLK
52
TXCLKMODE
50
TXCPSEL
TXCRCCLOCKDOUBLE 49
TXCRCSAMECLOCK 49
50
TXDAT_TAP_DAC
59
TXDATA_SEL
TXFDCAL_CLOCK_DIVIDE
TXFDET_CLOCK_DIVIDE 50
51
TXHIGHSIGNALEN
52
TXOUTCLK1_USE_SYNC
52
TXOUTDIV2SEL
TXPD 52
TXPHASESEL 52
52
TXPLLNDIVSEL
51
TXPOST_TAP_DAC
51
TXPOST_TAP_PD
TXPRE_TAP_DAC 51
TXPRE_TAP_PD 51
51
TXSLEWRATE
51
TXTERMTRIM
50
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