Differential Receiver; Clock And Data Recovery - Xilinx Virtex-4 RocketIO User Manual

Chapter 4: PMA Analog Design Considerations
Figure 4-7: RX after 36 Inches FR4 and Maximal Pre-Emphasis

Differential Receiver

The differential receiver accepts the V
calculation V
All input data must be differential and nominally biased to a common mode voltage of
0.25 V – 2.5V or AC coupled. Internal terminations provide for simple 50Ω transmission
line connection.
The differential receiver parameters are shown in the RocketIO DC Specifications and the
RocketIO Receiver Switching Characteristics in the Virtex-4 Data Sheet.

Clock and Data Recovery

The serial MGT input is locked to the input data stream through Clock and Data Recovery
(CDR), a built-in feature of the MGT. CDR keys off of the rising and falling edges of
incoming data and derives a clock that is representative of the incoming data rate.
The derived clock, RXRECCLK1/RXRECCLK2, is generated and locked to as long as it
remains within the specified component range. This clock is presented to the FPGA fabric
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P
-V electronically.
P N
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and V signals, carrying out the difference
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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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