Mgt Ports That Cannot Be Simulated; Txbufferr - Xilinx Virtex-4 RocketIO User Manual

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MGT Ports that Cannot Be Simulated

These MGT ports cannot be simulated by digital simulators such as ModelSim:
Note:

TXBUFFERR

If an assertion of TXBUFFERR occurs, it is most likely that the clock attributes were set
incorrectly.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
USER_8B_RX_DATA [31:24] → RX_DATA [7:0]
USER_8B_RX_DATA [23:16] → RX_DATA [15:8]
USER_8B_RX_DATA [15:8] → RX_DATA [23:16]
USER_8B_RX_DATA [7:0] → RX_DATA [31:24]
♦
RXMCLK
♦
TXSYNC
♦
RXSYNC
RXMCLK clock port is not supported.
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SmartModel Simulation Considerations
185