Xilinx Virtex-4 RocketIO User Manual page 310

Appendix C: Dynamic Reconfiguration Port
Table C-18: Dynamic Reconfiguration Port Memory Map: MGTB Address 4F–53
Bit
4F Def
15
14
13
12
11
10
9
8
RESERVED TXCRCINITVAL
N/A
[15:0]
7
6
5
4
3
2
1
0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
310
50 Def 51
RESERVED
[14:0]
N/A
[15:0]
(2)
RXCPSEL
Table C-28, page 320 for details.
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Address
(1)
Def 52
RESERVED
[5:0]
N/A
COMMA_10B_MASK
[9:0]
X
Def 53
RXFDCAL_CLOCK_DIVIDE
[1:0]
TXFDCAL_CLOCK_DIVIDE
[1:0]
RXBY_32
RESERVED
ENABLE_DCDR
SAMPLE_8X
N/A
DCDR_FILTER
(2)
[2:0]
RXUSRDIVISOR
[4:0]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
N/A
0
0
0
N/A