Xilinx Virtex-4 RocketIO User Manual page 71

R
Table 2-6: RX PMA Attribute Values
Notes:
1. See
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Attribute
RXPLLNDIVSEL
RXOUTDIV2SEL
RXUSRDIVISOR
RXCLKMODE
RXASYNCDIVIDE
DIGRX_FWDCLK
RXRECCLK1_USE_SYNC
Figure 2-11 for application-specific settings.
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(1)
Available
Values
Receive PLL feedback divide. This value
becomes the PLL multiplication factor for the
reference clock.
Receiver PLL output divide. DRP values are:
8, 10, 16, 20,
40 = 1010
16, 32, 40
32 = 1000
20 = 0110
16 = 0100
10 = 0010
8 = 0000
RXOUTDIV2SEL value = DRP value:
1 = 0001
2 = 0010
1, 2, 4, 8, 16, 32
4 = 0011
8 = 0100
16 = 0101
32 = 0110
Selects the divisor for the clock received from
the PMA. The divided clock becomes
RXRECCLK1. See
RXUSRDIVISOR value = DRP value:
1, 2, 4, 8, 16
1 = 00001
2 = 00010
4 = 00100
8 = 01000
16 = 10000
See Figure 2-12 Selects receiver output clocks and 32- or 40-bit
and PMA output data path width. See
Figure 2-11 Clocking Options"
Asynchronous Divider Ratios:
00= Divide by 1
00, 01,
01= Divide by 2
10, 11
10= Divide by 4
11= Divide by 4
00= 1XCLK (4-byte clock)
00, 01,
01= 2XCLK (2-byte clock)
10, 11
10= 4XCLK (1-byte clock)
FALSE:
RXRECCLK1 = synchronous PCS RXCLK
FALSE/TRUE
TRUE:
RXRECCLK1 = asynchronous PCS RXCLK
Clock Distribution
Definition
Figure 2-5.
"Setting the
for correct settings.
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