Memory Map - Xilinx Virtex-4 RocketIO User Manual

Appendix C: Dynamic Reconfiguration Port
See the figures entitled "Write Timing with Wait States" and "Read Timing with Wait
States" in the Virtex-4 Configuration Guide (UG071).

Memory Map

The configuration registers are 16- bit byte-wide and memory mapped based on
DADDR[7:0]. The memory assignment and resistor layout for MGTA are shown in
Table C-2
shown in
Table C-2: Dynamic Reconfiguration Port Memory Map: MGTA Address 40–44
Bit
40 Def
15
14
13
12
11
10
9
8
RXCRCINITVAL
N/A
[15:0]
7
6
5
4
3
2
1
0
294
through Table C-14. The memory assignment and resistor layout for MGTB are
Table C-15 through
41 Def
RESERVED
RESERVED
N/A
[15:0]
COMMA32
PCOMMA_DETECT
MCOMMA_DETECT
DEC_VALID_COMMA_ONLY
DEC_PCOMMA_DETECT
DEC_MCOMMA_DETECT
ALIGN_COMMA_WORD
www.xilinx.com
Table C-27. Table C-28 shows the PLL configuration settings.
Address
42 Def
CLK_COR__8B10B_DE
CLK_CORRECT_USE
CLK_COR_SEQ_LEN
[7:0]
CLK_COR_SEQ_DROP
CLK_COR_SEQ_2_USE
N/A
TXCLK0_INVERT_PMALEAF
CLK_COR_MAX_LAT
[1:0]
43 Def 44
RESERVED
[2:0]
RESERVED
[14:0]
N/A
RESERVED
[5:0]
TXPD
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
0