Xilinx Virtex-4 RocketIO User Manual page 338

46
TXBUFERR
TXBYPASS8B10B 44
TXCALFAIL 41
44
TXCHARDISPMODE
44 110
TXCHARDISPVAL
,
45 111
TXCHARISK
,
TXCLKSTABLE 41
40
TXCRCCLK
40
TXCRCDATAVALID
40
TXCRCDATAWIDTH
TXCRCIN 40
TXCRCINIT 40
40
TXCRCINTCLK
40
TXCRCOUT
40
TXCRCPD
TXCRCRESET 40
TXCYCLELIMIT 41
45
TXDATA
46
TXDATAWIDTH
43
TXENC64B66BUSE
TXENC8B10BUSE 45
TXENOOB 43
TXGEARBOX64B66BUSE
41
TXINHIBIT
46
TXINTDATAWIDTH
TXKERR 45 111
,
42
TXLOCK
41
TXN
42
TXOUTCLK1
TXOUTCLK2 42
TXP 41
42
TXPCSHCLKOUT
42
TXPMARESET
41
TXPOLARITY
TXRESET 46
TXRUNDISP 45 111
,
43
TXSYNC
46
TXUSRCLK
46
TXUSRCLK2
Ports, Clock
64 65
GREFCLK ,
64 65
REFCLK1
,
64 65
REFCLK2
,
RXCRCCLK 64
RXCRCINTCLK 64
64
RXMCLK
64
RXPCSHCLKOUT
64
RXRECCLK1
RXRECCLK2 64
RXUSRCLK 64
64
RXUSRCLK2
64
TXCRCCLK
338
TXCRCINTCLK
TXOUTCLK1
TXOUTCLK2
110
, TXPCSHCLKOUT
TXUSRCLK
TXUSRCLK2
Ports, CRC
RXCRCCLK
RXCRCDATAVALID
RXCRCDATAWIDTH
RXCRCIN
RXCRCINIT
RXCRCINTCLK
RXCRCOUT
RXCRCPD
RXCRCRESET
TXCRCCLK
TXCRCDATAVALID
TXCRCDATAWIDTH
TXCRCIN
TXCRCINIT
TXCRCINTCLK
43
TXCRCOUT
TXCRCPD
TXCRCRESET
Ports, Low-Latency
LOOPBACK(0)
RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDEC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXSYNC
TXENC64B66BUSE
TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXSCRAM64B66BUSE
TXSYNC
Power Conditioning
Power Control Description (table)
Power Down
Power Filtering Network for One Trans-
ceiver 167
Power Filtering Network for One Trans-
ceiver (figure)
Power Supply Circuit (figure)
Power Supply Circuit Using LT1963
(LT1963A) Regulator (figure)
Power Supply Filtering
Powering RocketIO MGTs
Filtering
Regulators
www.xilinx.com
64
64
64
64
64
64
153
153
153
153
153
153
153
153
153
153
154
154
154
154
154
154
154
154
196
196
196
196
196
196
196
197
197
197
197
197
163
151
151
167
166
166
328
236
236
236
168
Powering Unused MGTs
Pre-emphasis 140
R
30
Random Jitter (RJ)
147
Receive Equalization
172
Receive Termination
Receive Termination (figure)
Receiver Lock Control 147
Receiving Vitesse Channel Bonding Se-
115
quence
152 236
Reference Clock
,
Sources 236
237
Traces
29
Related Information
Reset Signals
RXCRCRESET 83 85
,
RXPMARESET 83
83 84
RXRESET ,
83 85
TXCRCRESET
,
83
TXPMARESET
TXRESET 83 84
,
Resets (MGT) 83
85
Resetting the Transceiver
Receive Reset Sequences
RX Reset Sequence Background
Transmit Reset Sequences
Rocket I/O Clock Descriptions (table)
271
RocketIO DCLK Switching Characteris-
276
tics (table)
RocketIO MGT
39
Instantiations
Timing Model 271
RocketIO MGT Block Diagram (figure)
RocketIO MGT CRC Attributes (table)
RocketIO MGT Digital Receiver Primitive
59
Attributes (table)
RocketIO MGT PCS Attributes (table)
RocketIO MGT PMA Attributes (table)
RocketIO MGT Reset Signals (table)
RocketIO MGT Timing Model
RocketIO RXCRCCLK Switching Charac-
276
teristics (table)
RocketIO RXUSRCLK Switching Charac-
teristics (table) 277
RocketIO TXCRCCLK Switching Charac-
277
teristics (table)
RocketIO TXUSRCLK Switching Charac-
teristics (table) 280
39 48 77 101
RocketIO Wizard , , ,
176
Routing Serial Traces
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
172
93 96 99
, ,
100
85 88
,
36
48
54
50
83
271