Xilinx Virtex-4 RocketIO User Manual page 188

Chapter 7: Simulation and Implementation
Table 7-5: LOC Grid and Package Pins Correlation for FF1517
LOC
Constraint
MGT
GT11_X0Y0 106B
GT11_X0Y1 106A
GT11_X0Y2
105B
GT11_X0Y3 105A
GT11_X0Y4 103B
GT11_X0Y5 103A
GT11_X0Y6 102B
GT11_X0Y7 102A
GT11_X0Y8 101B
GT11_X0Y9 101A
GT11_X0Y10 –
GT11_X0Y11 –
GT11_X1Y0
109B
GT11_X1Y1 109A
GT11_X1Y2 110B
GT11_X1Y3 110A
GT11_X1Y4 112B
GT11_X1Y5 112A
GT11_X1Y6 113B
GT11_X1Y7 113A
GT11_X1Y8 114B
GT11_X1Y9 114A
GT11_X1Y10
–
GT11_X1Y11 –
188
XC4VFX100-FF1517
TXP TXN RXP
AW25 AW24 AW22
AW28 AW27 AW31
AT39 AU39 AW37
AP39 AR39 AL39
P39 R39 U39
M39 N39 J39
A36 A37 C39
A34 A35 A31
A26 A27 A29
A24 A25 A21
– – –
– – –
AW15 AW16 AW18
AW12 AW13 AW9
AT1 AU1 AW3
AP1 AR1 AL1
P1 R1 U1
M1 N1 J1
A4 A3 C1
A6 A5 A9
A14 A13 A11
A16 A15 A19
– – –
– – –
www.xilinx.com
XC4VFX140-FF1517
RXN MGT TXP
AW21 106B AW25
AW30 106A AW28
AW36 105B AT39
AM39 105A AP39
V39 104B AE39
K39 104A AC39
D39 103B P39
A32 103A M39
A30 102B A36
A22 102A A34
– 101B A26
– 101A A24
AW19 109B AW15
AW10 109A AW12
AW4 110B AT1
AM1 110A AP1
V1 111B AE1
K1 111A AC1
D1 112B P1
A8 112A M1
A10 113B A4
A18 113A A6
– 114B A14
– 114A A16
TXN RXP RXN
AW24 AW22 AW21
AW27 AW31 AW30
AU39 AW37 AW36
AR39 AL39 AM39
AF39 AH39 AJ39
AD39 Y39 AA39
R39 U39 V39
N39 J39 K39
A37 C39 D39
A35 A31 A32
A27 A29 A30
A25 A21 A22
AW16 AW18 AW19
AW13 AW9 AW10
AU1 AW3 AW4
AR1 AL1 AM1
AF1 AH1 AJ1
AD1 Y1 AA1
R1 U1 V1
N1 J1 K1
A3 C1 D1
A5 A9 A8
A13 A11 A10
A15 A19 A18
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R