Xilinx Virtex-4 RocketIO User Manual page 49

R
Table 1-10: RocketIO MGT CRC Attributes (Continued)
Attribute
RXCRCINVERTGEN
TXCRCCLOCKDOUBLE
TXCRCINITVAL
TXCRCSAMECLOCK
TXCRCENABLE
TXCRCINVERTGEN
Notes:
1. RapidIO uses a 16-bit CRC, which cannot be generated or checked using the MGT's CRC-32 block.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Type
FALSE/TRUE. Inverts the receiver CRC clock.
FALSE: CRC clock not inverted.
Boolean
TRUE: CRC clock inverted.
During normal operation, this should always be set to FALSE.
FALSE/TRUE. Select clock frequency ratio between TXCRCCLK and
TXCRCINTCLK.
FALSE: Both clocks are at the same frequency.
Boolean
TRUE: The fabric data interface clock TXCRCINTCLK is
operating at half the frequency of the internal clock TXCRCCLK.
See Chapter 5, "Cyclic Redundancy Check (CRC),"
Sets the transmitter CRC initial value. This must be defined for each
protocol that uses 32-bit CRC:
Protocol
Ethernet
32-bit
PCI-Express
Hex
Infiniband
Fibre Channel
Serial ATA
(1)
RapidIO
FALSE/TRUE. Selects single clock mode for TX CRC.
FALSE: The clocks are being supplied to both the TXCRCCLK and
TXCRCINTCLK ports.
TRUE: The fabric interface clock rate is the same as the internal
Boolean
clock rate (TXCRCCLOCKDOUBLE is FALSE); the CRC fabric
interface and internal logic are being clocked using
TXCRCINTCLK. This attribute is typically set to TRUE when
TXCRCCLOCKDOUBLE is set to FALSE.
See Chapter 5, "Cyclic Redundancy Check (CRC),"
FALSE/TRUE. Enables the TX CRC block.
Boolean
FALSE: TX CRC disabled.
TRUE: TX CRC enabled.
FALSE/TRUE. Inverts the transmitter CRC clock.
FALSE: CRC clock not inverted.
Boolean
TRUE: CRC clock inverted.
During normal operation, this should always be set to FALSE.
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Description
for more details.
Default
32'h FFFF FFFF
32'h 0000 0000
32'h 5232 5032
for more details.
Attributes
Init Value
N/A
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