Xilinx Virtex-4 RocketIO User Manual page 41

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Table 1-5: RocketIO MGT PMA Ports
Port
Calibration
RXCALFAIL
RXCLKSTABLE
RXCYCLELIMIT
TXCALFAIL
TXCLKSTABLE
TXCYCLELIMIT
Driver/Buffers
TXINHIBIT
RXPOLARITY
TXPOLARITY
RXN
RXP
TXN
TXP
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
I/O Port Size
O 1 Reserved. This calibration port is not supported.
When set to a logic 1, indicates the clocks are stable and MGT RX
I 1 calibration can start. See
Resets,"
O 1 Reserved. This calibration port is not supported.
O 1 Reserved. This calibration port is not supported.
When set to a logic 1, indicates that the clocks are stable and
I 1 MGT TX calibration can start. See
and Resets,"
O 1 Reserved. This calibration port is not supported.
When set to a logic 1, the TX differential pairs are forced to be a
I 1
constant 1/0. TXN = 1, TXP = 0
Inverts the polarity of the parallel RX data at the interface of the
I 1 PMA and PCS. Receive data is inverted when set to logic 1.
Parallel loopback data is affected by this port.
Inverts the polarity of the parallel TX data at the interface of the
I 1 PMA and PCS. Transmit data is inverted when set to logic 1.
Parallel loopback data is affected by this port.
Differential serial input (external package pin). See
I 1 "Simulation and Implementation,"
to MGT location constraint.
Differential serial input (external package pin). See
I 1 "Simulation and Implementation,"
to MGT location constraint.
Differential serial output (external package pin). See
O 1 "Simulation and Implementation,"
to MGT location constraint.
Differential serial output (external package pin). See
O 1 "Simulation and Implementation,"
to MGT location constraint.
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Definition
Chapter 2, "Clocking, Timing, and
for details.
Chapter 2, "Clocking, Timing,
for details.
Available Ports
Chapter 7,
for package pin correlation
Chapter 7,
for package pin correlation
Chapter 7,
for package pin correlation
Chapter 7,
for package pin correlation
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