Xilinx Virtex-4 RocketIO User Manual page 299

R
Table C-7: Dynamic Reconfiguration Port Memory Map: MGTA Address 59–5D
Bit
59 Def
15
14
13
12
11
10
9
8
RESERVED RESERVED
N/A
[15:0]
7
6
5
4
3
2
1
0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
5A Def
RXRECCLK1_USE_SYNC
TXOUTCLK1_USE_SYNC
TXCLK0_FORCE_PMACLK
RXCLK0_FORCE_PMACLK
TX_CLOCK_DIVIDER
[1:0]
RX_CLOCK_DIVIDER
[1:0]
N/A
[15:0]
TXCRCENABLE
RESERVED
TXCRCINVERTGEN
TXCRCCLOCKDOUBLE
RXCRCENABLE
RESERVED
RXCRCINVERTGEN
RXCRCCLOCKDOUBLE
Table C-28, page 320 for details.
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Address
5B Def
TXPRE_PRDRV_DAC
N/A
TXPRE_TAP_DAC
Memory Map
(1)
5C Def
0
0
RESERVED
0
[4:0]
0
0
1
1
(2)
[2:0]
1
UNUSED
TXPRE_TAP_PD 1
0
[4:3]
0
RESERVED 0
X
X
TXCLKMODE
[3:0]
X
X
5D Def
0
0
0
0
0
0
0
0
[15:0]
0
0
0
0
0
0
0
0
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