Xilinx Virtex-4 RocketIO User Manual page 336

50
VCODAC_INIT
Attributes, CRC
RXCRCCLKDOUBLE 154
154
RXCRCENABLE
154
RXCRCINITVAL
154
RXCRCSAMECLOCK
RXINVERTGEN 154
155
TXCRCCLKDOUBLE
155
TXCRCENABLE
155
TXCRCINITVAL
TXCRCSAMECLOCK 155
TXINVERTGEN 155
Attributes, Low-Latency
196
PMA_BIT_SLIP
196
RX_BUFFER_USE
RX_CLOCK_DIVIDER 196
RXCLK0_FORCE_PMACLK
196
RXDATA_SEL
197
TX_BUFFER_USE
197
TX_CLOCK_DIVIDER
TXCLK0_FORCE_PMACLK
TXDATA_SEL 197
197
TXPHASESEL
Attributes, RX PMA Clocking Values
Attributes, TX PMA Clocking Values
B
Basic Architecture and Capabilities
255
BGA Packages
273
Block Diagram, MGT
328
Board Guidelines
Bus Interface 103
60
Byte Mapping
C
244
Cable
244
Connectors
Length, optimal 244
Skew between conductors
CCCB_ARBITRATOR_DISABLE
CHAN_BOND_SEQ_1_MASK,
CHAN_BOND_SEQ_2_MASK,
CHAN_BOND_SEQ_LEN
Channel Bond Alignment Sequence (ta-
127
ble)
Channel Bonding 127
CLK_COR_SEQ_1_MASK,
CLK_COR_SEQ_2_MASK,
CLK_COR_SEQ_LEN 125
146
Clock and Data Recovery
123
Clock Correction
336
Clock Correction Mask Example Settings
(Mask Enabled) (table)
Clock Correction Mask Example Settings
(No Mask)
Clock Correction Sequence/Data Correla-
tion for 16-Bit Data Port (table)
Clock Correction Sequences
Clock Ports see Ports, Clock
Clocking and Timing Considerations
Clocking, Timing, and Resets
Comma Detection
116
Bypass
SONET Alignment
Summary
Communications Standards Supported
by the MGT (table)
Control/Status Bus Association to Data
Bus Byte Paths (table)
196
237
Coupling
237
AC
237
DC
External capacitor value
197
CRC Attributes
RXCRCENABLE
RXCRCINITVAL
71
RXINVERTGEN
69
TXCRCENABLE
TXCRCINITVAL
TXINVERTGEN
CRC Attributes see Attributes, CRC
35
CRC Ports see Ports, CRC
CRC Primitive Ports (table)
CRC_32 Inputs and Outputs (figure)
CREFCLK and GREFCLK Options for an
MGT Tile (figure)
Cyclic Redundancy Check (CRC)
D
Data characters, valid (table)
DC-Coupled Serial Link
DC-Coupled Serial Link (figure)
244
DEC_MCOMMA_DETECT
129
DEC_PCOMMA_DETECT
Definition (table)
Deserializer Comma Detection Bypass
130
(table) 116
Design Migration
Introduction
Primary Differences
Virtex-II Pro to Virtex-II Pro X FPGA
321 325
,
Determining Correct
CLK_COR_MIN_LAT
www.xilinx.com
126
125
125
124
61
61
116
119
116
35
60
237
48
48
49
49
49
49
40
153
67
153
283
173
173
118
118
147
325
325
126
30
Deterministic Jitter (DJ)
Device Implementation
XC2VPX20, XC4VFX60 131
Differential Amplifier (figure)
146
Differential Receiver
177
Differential Trace Design
Differential Transmitter 139
250
Differential Vias
130
Disable Channel Bonding
293
Dynamic Configuration Bus
E
Encoding/Decoding 104
Event Indication 133
156
Examples
Examples of Data Rates for CRC Calcula-
tion (table) 156
Excess Capacitance and Inductance
External Bus Width Configuration (Fabric
103
Interface)
F
Functionality (CRC-32) 155
G
Global Signal Primitive Ports
Global Signal Primitive Ports (table)
H
High-Speed Serial Trace Design
I
Interface Description 293
Internal Bus Width Configuration
235
Introduction
J
30
Jitter Definition
Johnson, Dr. Howard 235
K
283
K-characters, valid (table)
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
139
245
47
47
174
104